The present invention relates to an error detection system for detecting errors which may occur in the processing of data by a logic unit.
The need for the accurate processing of digital data is well known in computer and automation technology. Most often, such digital data is represented or coded into sequences of binary signals (hereinafter referred to as bits). Each position in such sequential code word consists of a bit "0" or "1", the different code word permutations of bits representing different items of information.
It is desirable in the processing of digital data to be able to detect when an error has occurred in the processing operation so that corrective action may be taken. One well known technique for determining when an error has occurred is to provide redundant data for comparing with the actual data, or redundant processing units whose output is compared with the actually used processing unit. When the comparison produces a discrepancy or a mismatch, then it is known that an error has occurred and the user of the system can be notified.
The above described arrangements can be quite costly because of the cost of equipment necessary for comparing real data bits with the redundant data bits, especially if it is desired to have such comparison performed in more than one location in the system. Then, not only must additional comparing units be provided, but data buses for carrying the redundant bits must also be provided.